To exploit the high data transmission rate of optical fibers, new circuit technologies and architectures are evolving. Digital communication systems which operate at these higher data rates require multiplexers (MUX) and demultiplexers (DEMUX) which operate in the several giga-bits-per-second (Gb/s) range. To achieve the optimum data speed, circuits must operate at the maximum NRZ (non-return-to-zero) data rate possible for the particular technology.
The effective and practical utilization of a MUX circuit in a communication system requires that a minimum number of adjustable delay lines be utilized. Undesirably, existing MUX circuits require one variable delay line to sync the external clock to the received data and one or more additional variable delay lines to sync the clocking of the various stages of the MUX.
Additionally, the MUX must be able to handle multiple channel data arriving simultaneously at the MUX inputs; otherwise, an additional variable delay line for each channel may be required to properly stagger the data to the MUX. Existing MUX designs have failed to meet all of the above objectives.